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Oct. 19th, 2011 04:33 pm![[personal profile]](https://www.dreamwidth.org/img/silk/identity/user.png){kind=small}
norian"When any company makes a new architecture, they peer in to the crystal ball, and come up with possible workloads for many different scenarios. An architecture is then designed, those workloads are run on simulated chips, and the results fed back in to the design. Data paths are widened, buffers enlarged, caches made more granular, and thousands of other changes are made. Or the opposite, some things are simply not used as much as predicted, and can be made smaller or more efficient. It is a somewhat iterative process.
After a while, choices are made, and designs are frozen. Since simulations are hard pressed to run a full core, much less a full core at MHz speeds, sub-sections of the chip are run, or units are simplified for speed. In any case, the number of CPU cycles that can be simulated for a complete core, much less a complete chip, are shockingly small."
by Charlie Demerjian
After a while, choices are made, and designs are frozen. Since simulations are hard pressed to run a full core, much less a full core at MHz speeds, sub-sections of the chip are run, or units are simplified for speed. In any case, the number of CPU cycles that can be simulated for a complete core, much less a complete chip, are shockingly small."
by Charlie Demerjian